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Complete symbolic simulation of SystemC models [electronic resource] : efficient formal verification of finite non-terminating programs

Complete symbolic simulation of SystemC models [electronic resource] : efficient formal verification of finite non-terminating programs

자료유형
E-Book(소장)
개인저자
Herdt, Vladimir.
서명 / 저자사항
Complete symbolic simulation of SystemC models [electronic resource] : efficient formal verification of finite non-terminating programs / Vladimir Herdt.
발행사항
Wiesbaden :   Springer Fachmedien Wiesbaden :   Imprint: Springer Vieweg,   c2016.  
형태사항
1 online resource (xix, 162 p.) : ill.
총서사항
BestMasters
ISBN
9783658126803
요약
In his master thesis, Vladimir Herdt presents a novel approach, called complete symbolic simulation, for a more efficient verification of much larger (non-terminating) SystemC programs. The approach combines symbolic simulation with stateful model checking and allows to verify safety properties in (cyclic) finite state spaces, by exhaustive exploration of all possible inputs and process schedulings. The state explosion problem is alleviated by integrating two complementary reduction techniques. Compared to existing approaches, the complete symbolic simulation works more efficiently, and therefore can provide correctness proofs for larger systems, which is one of the most challenging tasks, due to the ever increasing complexity. Contents Verification of Systems Introduction to Formal Verification of SystemC Models Symbolic Model Checking with Partial Order Reduction Efficient Symbolic State Matching using State Subsumption Heuristic Approaches for Symbolic State Matching Evaluation of Proposed Techniques Target Groups Lecturers and Students of Computer Sciences and Electrical Engineering Hardware Designers and Verification Engineers using SystemC The Author Vladimir Herdt is working as Research Assistant in the Group of Computer Architecture at the University of Bremen, where he is pursuing his PhD degree.
일반주기
Title from e-Book title page.  
내용주기
Verification of Systems -- Introduction to Formal Verification of SystemC Models -- Symbolic Model Checking with Partial Order Reduction -- Efficient Symbolic State Matching using State Subsumption -- Heuristic Approaches for Symbolic State Matching -- Evaluation of Proposed Techniques.
서지주기
Includes bibliographical references.
이용가능한 다른형태자료
Issued also as a book.  
일반주제명
Formal methods (Computer science). Computer software --Verification.
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020 ▼a 9783658126803
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100 1 ▼a Herdt, Vladimir.
245 1 0 ▼a Complete symbolic simulation of SystemC models ▼h [electronic resource] : ▼b efficient formal verification of finite non-terminating programs / ▼c Vladimir Herdt.
260 ▼a Wiesbaden : ▼b Springer Fachmedien Wiesbaden : ▼b Imprint: Springer Vieweg, ▼c c2016.
300 ▼a 1 online resource (xix, 162 p.) : ▼b ill.
490 1 ▼a BestMasters
500 ▼a Title from e-Book title page.
504 ▼a Includes bibliographical references.
505 0 ▼a Verification of Systems -- Introduction to Formal Verification of SystemC Models -- Symbolic Model Checking with Partial Order Reduction -- Efficient Symbolic State Matching using State Subsumption -- Heuristic Approaches for Symbolic State Matching -- Evaluation of Proposed Techniques.
520 ▼a In his master thesis, Vladimir Herdt presents a novel approach, called complete symbolic simulation, for a more efficient verification of much larger (non-terminating) SystemC programs. The approach combines symbolic simulation with stateful model checking and allows to verify safety properties in (cyclic) finite state spaces, by exhaustive exploration of all possible inputs and process schedulings. The state explosion problem is alleviated by integrating two complementary reduction techniques. Compared to existing approaches, the complete symbolic simulation works more efficiently, and therefore can provide correctness proofs for larger systems, which is one of the most challenging tasks, due to the ever increasing complexity. Contents Verification of Systems Introduction to Formal Verification of SystemC Models Symbolic Model Checking with Partial Order Reduction Efficient Symbolic State Matching using State Subsumption Heuristic Approaches for Symbolic State Matching Evaluation of Proposed Techniques Target Groups Lecturers and Students of Computer Sciences and Electrical Engineering Hardware Designers and Verification Engineers using SystemC The Author Vladimir Herdt is working as Research Assistant in the Group of Computer Architecture at the University of Bremen, where he is pursuing his PhD degree.
530 ▼a Issued also as a book.
538 ▼a Mode of access: World Wide Web.
650 0 ▼a Formal methods (Computer science).
650 0 ▼a Computer software ▼x Verification.
830 0 ▼a BestMasters.
856 4 0 ▼u https://oca.korea.ac.kr/link.n2s?url=http://dx.doi.org/10.1007/978-3-658-12680-3
945 ▼a KLPA
991 ▼a E-Book(소장)

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