HOME > 상세정보

상세정보

Fundamentals of computer architecture and design [electronic resource]

Fundamentals of computer architecture and design [electronic resource]

자료유형
E-Book(소장)
개인저자
Bindal, Ahmet.
서명 / 저자사항
Fundamentals of computer architecture and design [electronic resource] / Ahmet Bindal.
발행사항
Cham :   Springer,   c2017.  
형태사항
1 online resource (xiv, 533 p.) : ill.
ISBN
9783319258096 9783319258119 (e-book)
요약
This textbook provides semester-length coverage of computer architecture and design, providing a strong foundation for students to understand modern computer system architecture and to apply these insights and principles to future computer designs.  It is based on the author’s decades of industrial experience with computer architecture and design, as well as with teaching students focused on pursuing careers in computer engineering.  Unlike a number of existing textbooks for this course, this one focuses not only on CPU architecture, but also covers in great detail in system buses, peripherals and memories.This book teaches every element in a computing system in two steps.  First, it introduces the functionality of each topic (and subtopics) and then goes into “from-scratch design” of a particular digital block from its architectural specifications using timing diagrams.  The author describes how the data-path of a certain digital block is generated using timin g diagrams, a method which most textbooks do not cover, but is valuable in actual practice.  In the end, the user is ready to use both the design methodology and the basic computing building blocks presented in the book to be able to produce industrial-strength designs. Provides semester-length textbook for students in computer and electrical engineering, covering the design of complex computing blocks from archite ctural specifications; Focuses not only on CPU architecture, but also covers in detail system buses, peripherals and memories; Presented in a manner catering to young engineering minds, this textbook minimizes text, while using a systematic design approach with architectural schematics, timing diagrams and control circuits; Includes extensive exercises and projects at the end of each chapter; Solutions to review problems and PowerPoint slides for instructors available.  
일반주기
Title from e-Book title page.  
내용주기
Review Of Combinational Circuits -- Review Of Sequential Circuits -- Review Of Asynchronous Circuits -- System Bus -- Memory Circuits And Systems -- Central Processing Unit -- System Peripherals -- Special Topics.
서지주기
Includes bibliographical references and index.
이용가능한 다른형태자료
Issued also as a book.  
일반주제명
Computer architecture. System design. Logic design.
바로가기
URL
000 00000cam u2200205 a 4500
001 000046012035
005 20200129133109
006 m d
007 cr
008 200107s2017 sz a ob 001 0 eng d
020 ▼a 9783319258096
020 ▼a 9783319258119 (e-book)
040 ▼a 211009 ▼c 211009 ▼d 211009
050 4 ▼a TK7888.4
082 0 4 ▼a 004.2/2 ▼2 23
084 ▼a 004.22 ▼2 DDCK
090 ▼a 004.22
100 1 ▼a Bindal, Ahmet.
245 1 0 ▼a Fundamentals of computer architecture and design ▼h [electronic resource] / ▼c Ahmet Bindal.
260 ▼a Cham : ▼b Springer, ▼c c2017.
300 ▼a 1 online resource (xiv, 533 p.) : ▼b ill.
500 ▼a Title from e-Book title page.
504 ▼a Includes bibliographical references and index.
505 0 ▼a Review Of Combinational Circuits -- Review Of Sequential Circuits -- Review Of Asynchronous Circuits -- System Bus -- Memory Circuits And Systems -- Central Processing Unit -- System Peripherals -- Special Topics.
520 ▼a This textbook provides semester-length coverage of computer architecture and design, providing a strong foundation for students to understand modern computer system architecture and to apply these insights and principles to future computer designs.  It is based on the author’s decades of industrial experience with computer architecture and design, as well as with teaching students focused on pursuing careers in computer engineering.  Unlike a number of existing textbooks for this course, this one focuses not only on CPU architecture, but also covers in great detail in system buses, peripherals and memories.This book teaches every element in a computing system in two steps.  First, it introduces the functionality of each topic (and subtopics) and then goes into “from-scratch design” of a particular digital block from its architectural specifications using timing diagrams.  The author describes how the data-path of a certain digital block is generated using timin g diagrams, a method which most textbooks do not cover, but is valuable in actual practice.  In the end, the user is ready to use both the design methodology and the basic computing building blocks presented in the book to be able to produce industrial-strength designs. Provides semester-length textbook for students in computer and electrical engineering, covering the design of complex computing blocks from archite ctural specifications; Focuses not only on CPU architecture, but also covers in detail system buses, peripherals and memories; Presented in a manner catering to young engineering minds, this textbook minimizes text, while using a systematic design approach with architectural schematics, timing diagrams and control circuits; Includes extensive exercises and projects at the end of each chapter; Solutions to review problems and PowerPoint slides for instructors available.  
530 ▼a Issued also as a book.
538 ▼a Mode of access: World Wide Web.
650 0 ▼a Computer architecture.
650 0 ▼a System design.
650 0 ▼a Logic design.
856 4 0 ▼u https://oca.korea.ac.kr/link.n2s?url=https://doi.org/10.1007/978-3-319-25811-9
945 ▼a KLPA
991 ▼a E-Book(소장)

소장정보

No. 소장처 청구기호 등록번호 도서상태 반납예정일 예약 서비스
No. 1 소장처 중앙도서관/e-Book 컬렉션/ 청구기호 CR 004.22 등록번호 E14018976 도서상태 대출불가(열람가능) 반납예정일 예약 서비스 M

컨텐츠정보

목차

CONTENTS
1 Review of Combinational Circuits = 1
 1.1 Logic Gates = 2
 1.2 Boolean Algebra = 8
 1.3 Designing Combinational Logic Circuits Using Truth Tables = 11
 1.4 Combinational Logic Minimization - Karnaugh Maps = 14
 1.5 Basic Logic Blocks = 20
 1.6 Combinational Mega Cells = 29
2 Review of Sequential Logic Circuits = 67
 2.1 D Latch = 67
 2.2 Timing Methodology Using D Latches = 69
 2.3 D Rip-Flop = 70
 2.4 Timing Methodology Using D Flip-Flops = 72
 2.5 Timing Violations = 73
 2.6 Register = 79
 2.7 Shift Register = 80
 2.8 Counter = 81
 2.9 Moore Machine = 83
 2.10 Mealy Machine = 87
 2.11 Controller Design : Moore Machine Versus Counter-Decoder Scheme = 90
 2.12 Memory = 94
 2.13 A Design Example Using Sequential Logic and Memory = 97
3 Review of Asynchronous Logic Circuits = 113
 3.1 S-R Latch = 113
 3.2 Fundamental-Mode Circuit Topology = 114
 3.3 Fundamental-Mode Asynchronous Logic Circuits = 115
 3.4 Asynchronous Timing Methodology = 123
 Reference = 131
4 System Bus = 133
 4.1 Parallel Bus Architectures = 133
 4.2 Basic Write Transfer = 138
 4.3 Basic Read Transfer = 140
 4.4 Bus Master Status Change = 142
 4.5 Bus Master Handshake = 145
 4.6 Arbiter = 145
 4.7 Bus Master Handover = 148
 4.8 Serial Buses = 149
5 Memory Circuits and Systems = 169
 5.1 Static Random Access Memory = 170
 5.2 Synchronous Dynamic Random Access Memory = 179
 5.3 Electrically-Erasable-Programmable-Read-Only-Memory = 201
 5.4 Flash Memory = 209
 5.5 Serial Rash Memory = 253
 References = 274
6 Central Processing Unit = 275
 6.1 RISC Instruction Formats = 275
 6.2 CPU Data-Path = 277
 6.3 Fixed-Point Register-to-Register Type ALU Instructions = 280
 6.4 Fixed-Point Immediate Type ALU Instructions = 292
 6.5 Data Movement Instructions = 298
 6.6 Program Control Instructions = 302
 6.7 Design Example Ⅰ : A Fixed-Point CPU with Four Instructions = 308
 6.8 Design Example Ⅱ : A Fixed-Point CPU with Eight Instructions = 313
 6.9 Floating-Point Instructions = 316
 6.10 Floating-Point = 317
 6.11 Floating-Point Adder = 322
 6.12 Floating-Point Multiplier = 324
 6.13 A RISC CPU with Fixed and Floating-Point Units = 325
 6.14 Structural Hazards = 327
 6.15 Data Hazards = 328
 6.16 Program Cntrol Hazards = 333
 6.17 Handling Hazards in a Five-Stage RISC CPU : An Example = 335
 6.18 Handling Hazards in a Four-Stage RISC CPU = 339
 6.19 Handling Hazards in a Three-Stage RISC CPU = 340
 6.20 Multi-cycle ALU and Related Data Hazards = 342
 6.21 Cache Topologies = 346
 6.22 Cache Write and Read Structures = 349
 6.23 A Direct-Mapped Cache Example = 351
 6.24 Write-Through and Write-Back Cache Structures in Set-Associative Caches = 354
 6.25 A Two-Way Set-Associative Write-Through Cache Example = 355
 6.26 A Two-Way Set-Associative Write-Back Cache Example = 358
 References = 375
7 System Peripherals = 377
 7.1 Overall System Arcitecture = 377
 7.2 Direct Memory Access Controller = 378
 7.3 Interrupt Controller = 387
 7.4 Serial Transmitter and Receiver Interface = 399
 7.5 Timers = 406
 7.6 Display Adaptor = 414
 7.7 Data Converters = 425
 7.8 Digital-to-Analog Converter (DAC) = 437
 References = 454
8 Special Topics = 455
 8.1 Field-Programmable-Gate Array = 455
 8.2 Data-Driven Processors = 473
 References = 489
Appendix : An Introduction to Verilog Hardware Design Language = 491
Index = 529

관련분야 신착자료

김종원 (2020)