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From variability tolerance to approximate computing in parallel integrated architectures and accelerators [electronic resource]

From variability tolerance to approximate computing in parallel integrated architectures and accelerators [electronic resource]

Material type
E-Book(소장)
Personal Author
Raḥīmī, ʿAbbās. Benini, Luca, 1967-. Gupta, Rajesh Kumar, 1961-.
Title Statement
From variability tolerance to approximate computing in parallel integrated architectures and accelerators [electronic resource] / Abbas Rahimi, Luca Benini, Rajesh K. Gupta.
Publication, Distribution, etc
Cham :   Springer,   2017.  
Physical Medium
1 online resource (xv, 197 p.) : ill. (some col.).
ISBN
9783319537689 (e-Book) 9783319537672
요약
This book focuses on computing devices and their design at various levels to combat variability. The authors provide a review of key concepts with particular emphasis on timing errors caused by various variability sources. They discuss methods to predict and prevent, detect and correct, and finally conditions under which such errors can be accepted; they also consider their implications on cost, performance and quality. Coverage includes a comparative evaluation of methods for deployment across various layers of the system from circuits, architecture, to application software. These can be combined in various ways to achieve specific goals related to observability and controllability of the variability effects, providing means to achieve cross layer or hybrid resilience. · Covers challenges and opportunities in identifying microelectronic variability and the resulting errors at various layers in the system abstraction; · Enables readers to assess how various levels of circuit and system design can mitigate the effects of variability; Demonstrates overall system architecture of what is now called “approximate computing” paradigm in massively parallel integrated architectures and accelerators.
General Note
Title from e-Book title page.  
Content Notes
Introduction -- Part 1. Predicting and Preventing Errors -- Instruction-Level Tolerance -- Sequence-Level Tolerance -- Procedure-Level Tolerance -- Kernel-Level Tolerance -- Hierarchically Focused Guardbanding -- Part 2. Detecting and Correcting Errors -- Work-Unit Tolerance -- Memristive-Based Associative Memory for Error Recovery -- Part 3. Accepting Errors -- Accuracy-Configurable OpenMP -- An Approximation Workflow for Exploiting Data-Level Parallelism in FPGA Acceleration -- Memristive-Based Associative Memory for Approximate Computational Reuse -- Spatial and Temporal Memoization -- Outlook.
Bibliography, Etc. Note
Includes bibliographical references and index.
이용가능한 다른형태자료
Issued also as a book.  
Subject Added Entry-Topical Term
Engineering. Computer architecture. Parallel processing (Electronic computers).
Short cut
URL
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020 ▼a 9783319537689 (e-Book)
020 ▼a 9783319537672
040 ▼a 211009 ▼c 211009 ▼d 211009
050 4 ▼a TK7888.4
082 0 4 ▼a 004.2/2 ▼2 23
084 ▼a 004.22 ▼2 DDCK
090 ▼a 004.22
100 1 ▼a Raḥīmī, ʿAbbās.
245 1 0 ▼a From variability tolerance to approximate computing in parallel integrated architectures and accelerators ▼h [electronic resource] / ▼c Abbas Rahimi, Luca Benini, Rajesh K. Gupta.
260 ▼a Cham : ▼b Springer, ▼c 2017.
300 ▼a 1 online resource (xv, 197 p.) : ▼b ill. (some col.).
500 ▼a Title from e-Book title page.
504 ▼a Includes bibliographical references and index.
505 0 ▼a Introduction -- Part 1. Predicting and Preventing Errors -- Instruction-Level Tolerance -- Sequence-Level Tolerance -- Procedure-Level Tolerance -- Kernel-Level Tolerance -- Hierarchically Focused Guardbanding -- Part 2. Detecting and Correcting Errors -- Work-Unit Tolerance -- Memristive-Based Associative Memory for Error Recovery -- Part 3. Accepting Errors -- Accuracy-Configurable OpenMP -- An Approximation Workflow for Exploiting Data-Level Parallelism in FPGA Acceleration -- Memristive-Based Associative Memory for Approximate Computational Reuse -- Spatial and Temporal Memoization -- Outlook.
520 ▼a This book focuses on computing devices and their design at various levels to combat variability. The authors provide a review of key concepts with particular emphasis on timing errors caused by various variability sources. They discuss methods to predict and prevent, detect and correct, and finally conditions under which such errors can be accepted; they also consider their implications on cost, performance and quality. Coverage includes a comparative evaluation of methods for deployment across various layers of the system from circuits, architecture, to application software. These can be combined in various ways to achieve specific goals related to observability and controllability of the variability effects, providing means to achieve cross layer or hybrid resilience. · Covers challenges and opportunities in identifying microelectronic variability and the resulting errors at various layers in the system abstraction; · Enables readers to assess how various levels of circuit and system design can mitigate the effects of variability; Demonstrates overall system architecture of what is now called “approximate computing” paradigm in massively parallel integrated architectures and accelerators.
530 ▼a Issued also as a book.
538 ▼a Mode of access: World Wide Web.
650 0 ▼a Engineering.
650 0 ▼a Computer architecture.
650 0 ▼a Parallel processing (Electronic computers).
700 1 ▼a Benini, Luca, ▼d 1967-.
700 1 ▼a Gupta, Rajesh Kumar, ▼d 1961-.
856 4 0 ▼u https://oca.korea.ac.kr/link.n2s?url=https://doi.org/10.1007/978-3-319-53768-9
945 ▼a KLPA
991 ▼a E-Book(소장)

Holdings Information

No. Location Call Number Accession No. Availability Due Date Make a Reservation Service
No. 1 Location Main Library/e-Book Collection/ Call Number CR 004.22 Accession No. E14015897 Availability Loan can not(reference room) Due Date Make a Reservation Service M

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