| 000 | 00000nam c2200205 c 4500 | |
| 001 | 000045953547 | |
| 005 | 20180919165845 | |
| 007 | ta | |
| 008 | 180629s2018 ulkd bmAC 000c eng | |
| 040 | ▼a 211009 ▼c 211009 ▼d 211009 | |
| 085 | ▼a 0510 ▼2 KDCP | |
| 090 | ▼a 0510 ▼b 6D36 ▼c 1087 | |
| 100 | 1 | ▼a 남상준 ▼g 南相俊 |
| 245 | 1 1 | ▼a (A) monolithic 3D integrated FPGA for convolutional neural network acceleration / ▼d 南相俊 |
| 260 | ▼a Seoul : ▼b Graduate School, Korea University, ▼c 2018 | |
| 300 | ▼a v, 21장 : ▼b 도표 ; ▼c 26 cm | |
| 500 | ▼a 지도교수: 정성우 | |
| 502 | 0 | ▼a 학위논문(석사)-- ▼b 고려대학교 대학원: ▼c 컴퓨터·전파통신공학과, ▼d 2018. 8 |
| 504 | ▼a 참고문헌: 장 18-19 | |
| 530 | ▼a PDF 파일로도 이용가능; ▼c Requires PDF file reader(application/pdf) | |
| 653 | ▼a Monolithic 3D ▼a Convolutional Neural Network ▼a Accelerator ▼a FPGA ▼a Performance | |
| 776 | 0 | ▼t A Monolithic 3D Integrated FPGA for Convolutional Neural Network Acceleration ▼w (DCOLL211009)000000081706 |
| 900 | 1 0 | ▼a Nam, Sang Jun, ▼e 저 |
| 900 | 1 0 | ▼a 정성우 ▼g 鄭盛宇, ▼e 지도교수 |
| 945 | ▼a KLPA |
Electronic Information
| No. | Title | Service |
|---|---|---|
| 1 | (A) monolithic 3D integrated FPGA for convolutional neural network acceleration (25회 열람) |
View PDF Abstract Table of Contents |
Holdings Information
| No. | Location | Call Number | Accession No. | Availability | Due Date | Make a Reservation | Service |
|---|---|---|---|---|---|---|---|
| No. 1 | Location Science & Engineering Library/Stacks(Thesis)/ | Call Number 0510 6D36 1087 | Accession No. 123059631 | Availability Available | Due Date | Make a Reservation | Service |
| No. 2 | Location Science & Engineering Library/Stacks(Thesis)/ | Call Number 0510 6D36 1087 | Accession No. 123059632 | Availability Available | Due Date | Make a Reservation | Service |
Contents information
Abstract
Monolithic 3D (M3D) integration has been recently introduced to overcome excessive 2D interconnect delay. Since M3D integration uses the extremely small size of monolithic inter-tier vias (MIVs), it is expected to significantly reduce 2D interconnect delay by replacing 2D interconnects with MIVs. In this paper, we propose an M3D integrated FPGA to improve the performance of convolutional neural network (CNN) accelerators, where the interconnect delay accounts for a considerable portion of the critical path delay for a processing element (PE). Our proposed M3D integrated FPGA reduces the footprint by partitioning the operators in PEs to multiple layers, which leads to significant interconnect delay reduction. Our study shows that our proposed M3D integrated FPGA reduces the 2D interconnect delay by up to 41.1%, which results in critical path delay reduction by up to 16.7% in a PE, compared to the conventional 2D integrated FPGA.
Table of Contents
Abstract i Table of Contents ii List of Figures iv List of Tables v 1. Introduction 1 2. Background 3 2.1 Convolutional Neural Networks 3 2.2 Monolithic 3D Integration 5 3. M3D Integrated FPGA Based Processing Element for CNN Acceleration 7 4. Experimental Environment 12 5. Experimental Results 14 6. Conclusion 17 References 18 감사의 글 20
