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Advances in computer systems architecture : 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007 : proceedings

Advances in computer systems architecture : 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007 : proceedings

Material type
단행본
Personal Author
Choi, Lynn. Paek, Yunheung. Cho, Sangyeun.
Title Statement
Advances in computer systems architecture : 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007 : proceedings / Lynn Choi, Yunheung Paek, Sangyeun Cho (eds.).
Publication, Distribution, etc
Berlin ;   New York :   Springer,   c2007.  
Physical Medium
xiii, 400 p. : ill. ; 24 cm.
Series Statement
Lecture notes in computer science,0302-9743 ; 4697
ISBN
9783540743088 (softcover : alk. paper) 3540743081 (softcover : alk. paper)
Bibliography, Etc. Note
Includes bibliographical references and index.
Subject Added Entry-Topical Term
Computer architecture --Congresses.
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001 000045889930
005 20200910164517
008 161206s2007 gw a b 101 0 eng d
010 ▼a 2007932678
020 ▼a 9783540743088 (softcover : alk. paper)
020 ▼a 3540743081 (softcover : alk. paper)
035 ▼a (KERIS)REF000013555516
040 ▼a DLC ▼c DLC ▼d DLC ▼d 211009
050 0 0 ▼a QA76.9.A73 ▼b A28 2007
082 0 0 ▼a 004.2/2 ▼2 23
084 ▼a 004.22 ▼2 DDCK
090 ▼a 004.22 ▼b A187a ▼c 12
111 2 ▼a ACSAC (Asia-Pacific Computer Systems Architecture Conference) ▼n (12th : ▼d 2007 : ▼c Seoul, Korea).
245 1 0 ▼a Advances in computer systems architecture : ▼b 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007 : proceedings / ▼c Lynn Choi, Yunheung Paek, Sangyeun Cho (eds.).
246 3 0 ▼a ACSAC 2007
260 ▼a Berlin ; ▼a New York : ▼b Springer, ▼c c2007.
300 ▼a xiii, 400 p. : ▼b ill. ; ▼c 24 cm.
490 1 ▼a Lecture notes in computer science, ▼x 0302-9743 ; ▼v 4697
504 ▼a Includes bibliographical references and index.
650 0 ▼a Computer architecture ▼v Congresses.
700 1 ▼a Choi, Lynn.
700 1 ▼a Paek, Yunheung.
700 1 ▼a Cho, Sangyeun.
830 0 ▼a Lecture notes in computer science ; ▼v 4697.
945 ▼a KLPA

Holdings Information

No. Location Call Number Accession No. Availability Due Date Make a Reservation Service
No. 1 Location Science & Engineering Library/Sci-Info(Stacks2)/ Call Number 004.22 A187a 12 Accession No. 121238319 Availability Available Due Date Make a Reservation Service B M

Contents information

Table of Contents

A Compiler Framework for Supporting Speculative Multicore Processors.- Power-Efficient Heterogeneous Multicore Technology for Digital Convergence.- StarDBT: An Efficient Multi-platform Dynamic Binary Translation System.- Unbiased Branches: An Open Problem.- An Online Profile Guided Optimization Approach for Speculative Parallel Threading.- Entropy-Based Profile Characterization and Classification for Automatic Profile Management.- Laplace Transformation on the FT64 Stream Processor.- Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation.- Evolution of NAND Flash Memory Interface.- FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs.- Exploiting Single-Usage for Effective Memory Management.- An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories.- An Effective Design of Master-Slave Operating System Architecture for Multiprocessor Embedded Systems.- Optimal Placement of Frequently Accessed IPs in Mesh NoCs.- An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips.- Performance of Keyword Connection Algorithm in Nested Mobility Networks.- Leakage Energy Reduction in Cache Memory by Software Self-invalidation.- Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters.- Runtime Performance Projection Model for Dynamic Power Management.- A Power-Aware Alternative for the Perceptron Branch Predictor.- Power Consumption and Performance Analysis of 3D NoCs.- A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels.- Bipartition Architecture for Low Power JPEG Huffman Decoder.- A SWP Specification for Sequential Image Processing Algorithms.- A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision.- FPGA-Accelerated Active Shape Model for Real-Time People Tracking.- Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures.- Synchronization Mechanisms on Modern Multi-core Architectures.- Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs.- Generalized Wormhole Switching: A New Fault-Tolerant Mathematical Model for Adaptively Wormhole-Routed Interconnect Networks.- Open Issues in MPI Implementation.- Implicit Transactional Memory in Kilo-Instruction Multiprocessors.- Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units.- A Bypass Mechanism to Enhance Branch Predictor for SMT Processors.- Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor.- Architectural Solution to Object-Oriented Programming.


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