상세정보

In current processor designs, energy efficiency is considered as significant as performance. DVFS (dynamic voltage and frequency scaling) is a hardware design technique for reducing the energy consumption of the processor, minimizing energy wastage by altering the frequency based on the performance required by the processor. A number of studies suggested a technique for reducing the energy consumption of a system by using DVFS. However, the results thereof were tailored as per the experimental environment, and thus, for applying the results to a new processor environment, the expected level of energy saving could not be achieved. 


In this study, SPEM (Simplified Processor Energy Model) has been suggested to overcome the limitations of the existing DVFS studies. SPEM is a model describing the energy relationship of the processor. SPEM creates an equation describing the relationship between the frequency and energy of the processor by using a multiple regression analysis. Because the multiple regression analysis is not dependent on certain hardware, it can create an energy model of a processor from the experimental data in various processor environments. The accuracy of the model made on the basis of the result of the multiple regression analysis was over 95%. When SPEM was used for DVFS, the SPEC benchmark showed an error within 5% as compared to the minimum consumed energy, and for an arbitrary program, it showed a maximum energy loss of 10.39%. 

In order to confirm the applicability of SPEM in various hardware, an energy model was created in two types of both Intel processors and ARM processors. Although the types of processors were different, SPEM created an energy model of each processor by using the same model derivation method. Here, the maximum error of the model was 5.38\%.

1 Introduction 1
1.1 Inter-TaskDVFSvs.Intra-TaskDVFS . . . . . . . . . 2
1.2 Scope of this study . . . . . . . . . . . . . . . . . . . . 4
2 Workload Prediction using Runlength Encoding for Rum- time Processor Power Management 6
2.1 Motivation......................... 6
2.2 RelatedWork ....................... 7
2.3 BackgroundofGPHT................... 9
2.4 LimitationsofGPHT................... 11
2.5 GPHTexwithrun-lengthencoding. . . . . . . . . . . . 13
2.6 Evaluation......................... 15
2.7 Discussoin ......................... 18
2.8 Summary.......................... 20
3 Simplified Processor Energy Model 21
3.1 Motivation......................... 21
3.2 Goal of Simplified Processor Energy Model . . . . . . . 24
3.3 RelatedWork ....................... 26
3.4 EvaluationEnvironmentforSPEM . . . . . . . . . . . 28
3.5 SPEMDerivation ..................... 30
3.6 ModelValidation ..................... 44
3.7 ModelEvaluation ..................... 53
3.8 ComparewithOtherDVFSMechanism . . . . . . . . . 56
3.9 Summary.......................... 57
4 Other Processor Evaluation Result 58
4.1 IvyBridge:Intel3rdGeneration . . . . . . . . . . . . . 59
4.2 ARMCortex-A53 ..................... 74
4.3 ARMCortex-A57 ..................... 86
4.4 Summary.......................... 94
5 Conclusion 95
Bibliography 100