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Cryptographic hardware and embedded systems--CHES 2005 : 7th international workshop, Edinburgh, UK, August 29-September 1, 2005 : proceedings

Cryptographic hardware and embedded systems--CHES 2005 : 7th international workshop, Edinburgh, UK, August 29-September 1, 2005 : proceedings

Material type
단행본
Personal Author
Rao, Josyula Ramachandra, 1962-. Sunar, Berk.
Title Statement
Cryptographic hardware and embedded systems--CHES 2005 : 7th international workshop, Edinburgh, UK, August 29-September 1, 2005 : proceedings / Josyula R. Rao, Berk Sunar (eds.).
Publication, Distribution, etc
Berlin ;   New York :   Springer,   c2005.  
Physical Medium
xiv, 458 p. : ill. ; 24 cm.
Series Statement
Lecture notes in computer science,0302-9743 ; 3659
ISBN
3540284745 (pbk. : alk. paper) 9783540284741 (pbk. : alk. paper)
General Note
Also issued online.
Bibliography, Etc. Note
Includes bibliographical references and index.
이용가능한 다른형태자료
Also issued online.  
Subject Added Entry-Topical Term
Embedded computer systems -- Congresses. Cryptography -- Congresses. Computer security -- Congresses.
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020 ▼a 3540284745 (pbk. : alk. paper)
020 ▼a 9783540284741 (pbk. : alk. paper)
035 ▼a (OCoLC)ocm61386652
035 ▼a (OCoLC)61386652
035 ▼a (KERIS)REF000012452751
040 ▼a OHX ▼c OHX ▼d BAKER ▼d CUS ▼d C$Q ▼d IQU ▼d DLC ▼d 211009
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082 0 0 ▼a 005.8/2 ▼2 22
090 ▼a 005.82 ▼b C524c ▼c 2005
111 2 ▼a CHES 2005 ▼d (2005 : ▼c Edinburgh, Scotland)
245 1 0 ▼a Cryptographic hardware and embedded systems--CHES 2005 : ▼b 7th international workshop, Edinburgh, UK, August 29-September 1, 2005 : proceedings / ▼c Josyula R. Rao, Berk Sunar (eds.).
246 3 0 ▼a CHES 2005
260 ▼a Berlin ; ▼a New York : ▼b Springer, ▼c c2005.
300 ▼a xiv, 458 p. : ▼b ill. ; ▼c 24 cm.
490 1 ▼a Lecture notes in computer science, ▼x 0302-9743 ; ▼v 3659
504 ▼a Includes bibliographical references and index.
530 ▼a Also issued online.
650 0 ▼a Embedded computer systems ▼v Congresses.
650 0 ▼a Cryptography ▼v Congresses.
650 0 ▼a Computer security ▼v Congresses.
700 1 ▼a Rao, Josyula Ramachandra, ▼d 1962-.
700 1 ▼a Sunar, Berk.
830 0 ▼a Lecture notes in computer science ; ▼v 3659.
945 ▼a KINS

Holdings Information

No. Location Call Number Accession No. Availability Due Date Make a Reservation Service
No. 1 Location Science & Engineering Library/Sci-Info(Stacks2)/ Call Number 005.82 C524c 2005 Accession No. 121186790 Availability Available Due Date Make a Reservation Service B M

Contents information

Table of Contents

Side Channels I.- Resistance of Randomized Projective Coordinates Against Power Analysis.- Templates as Master Keys.- A Stochastic Model for Differential Side Channel Cryptanalysis.- Arithmetic for Cryptanalysis.- A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis.- Further Hidden Markov Model Cryptanalysis.- Low Resources.- Energy-Efficient Software Implementation of Long Integer Modular Arithmetic.- Short Memory Scalar Multiplication on Koblitz Curves.- Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051 ?P.- Special Purpose Hardware.- SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers.- Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization.- Design of Testable Random Bit Generators.- Hardware Attacks and Countermeasures I.- Successfully Attacking Masked AES Hardware Implementations.- Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints.- Masking at Gate Level in the Presence of Glitches.- Arithmetic for Cryptography.- Bipartite Modular Multiplication.- Fast Truncated Multiplication for Cryptographic Applications.- Using an RSA Accelerator for Modular Inversion.- Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings.- Side Channel II (EM).- EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA.- Security Limits for Compromising Emanations.- Security Evaluation Against Electromagnetic Analysis at Design Time.- Side Channel III.- On Second-Order Differential Power Analysis.- Improved Higher-Order Side-Channel Attacks with FPGA Experiments.- Trusted Computing.- Secure Data Management in Trusted Computing.- Hardware Attacks and Countermeasures II.- Data Remanence in Flash Memory Devices.- Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment.- Hardware Attacks and Countermeasures III.- DPA Leakage Models for CMOS Logic Circuits.- The "Backend Duplication" Method.- Efficient Hardware I.- Hardware Acceleration of the Tate Pairing in Characteristic Three.- Efficient Hardware for the Tate Pairing Calculation in Characteristic Three.- Efficient Hardware II.- AES on FPGA from the Fastest to the Smallest.- A Very Compact S-Box for AES.


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