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Cryptographic hardware and embedded systems--CHES 2006 : 8th international workshop, Yokohama, Japan, October 10-13, 2006 : proceedings

Cryptographic hardware and embedded systems--CHES 2006 : 8th international workshop, Yokohama, Japan, October 10-13, 2006 : proceedings (Loan 1 times)

Material type
단행본
Personal Author
Goubin, Louis. Matsui, Mitsuru, 1961-.
Title Statement
Cryptographic hardware and embedded systems--CHES 2006 : 8th international workshop, Yokohama, Japan, October 10-13, 2006 : proceedings / Louis Goubin, Mitsuru Matsui (eds.).
Publication, Distribution, etc
Berlin ;   New York :   Springer,   c2006.  
Physical Medium
xiv, 462 p. : ill. ; 24 cm.
Series Statement
Lecture notes in computer science,0302-9743 ; 4249
ISBN
3540465596 (pbk. : alk. paper) 9783540465591 (pbk. : alk. paper)
Bibliography, Etc. Note
Includes bibliographical references and index.
Subject Added Entry-Topical Term
Embedded computer systems -- Congresses. Cryptography -- Congresses. Computer security -- Congresses.
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020 ▼a 3540465596 (pbk. : alk. paper)
020 ▼a 9783540465591 (pbk. : alk. paper)
035 ▼a (OCoLC)ocm73108977
035 ▼a (OCoLC)73108977
035 ▼a (KERIS)REF000012962001
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072 7 ▼a TK ▼2 lcco
082 0 4 ▼a 005.8/2 ▼2 22
090 ▼a 005.82 ▼b C524c ▼c 2006
111 2 ▼a CHES 2006 ▼d (2006 : ▼c Yokohama, Japan)
245 1 0 ▼a Cryptographic hardware and embedded systems--CHES 2006 : ▼b 8th international workshop, Yokohama, Japan, October 10-13, 2006 : proceedings / ▼c Louis Goubin, Mitsuru Matsui (eds.).
246 3 0 ▼a CHES 2006
260 ▼a Berlin ; ▼a New York : ▼b Springer, ▼c c2006.
300 ▼a xiv, 462 p. : ▼b ill. ; ▼c 24 cm.
490 1 ▼a Lecture notes in computer science, ▼x 0302-9743 ; ▼v 4249
490 1 ▼a LNCS sublibrary. SL 4, Security and cryptology
504 ▼a Includes bibliographical references and index.
650 0 ▼a Embedded computer systems ▼v Congresses.
650 0 ▼a Cryptography ▼v Congresses.
650 0 ▼a Computer security ▼v Congresses.
700 1 ▼a Goubin, Louis.
700 1 ▼a Matsui, Mitsuru, ▼d 1961-.
830 0 ▼a Lecture notes in computer science ; ▼v 4249.
830 0 ▼a LNCS sublibrary. ▼n SL 4, ▼p Security and cryptology.
945 ▼a KINS

Holdings Information

No. Location Call Number Accession No. Availability Due Date Make a Reservation Service
No. 1 Location Science & Engineering Library/Sci-Info(Stacks2)/ Call Number 005.82 C524c 2006 Accession No. 121186791 Availability Available Due Date Make a Reservation Service B M

Contents information

Table of Contents

Side Channels I.- Template Attacks in Principal Subspaces.- Templates vs. Stochastic Methods.- Towards Security Limits in Side-Channel Attacks.- Low Resources.- HIGHT: A New Block Cipher Suitable for Low-Resource Device.- Invited Talk I.- Integer Factoring Utilizing PC Cluster.- Hardware Attacks and Countermeasures I.- Optically Enhanced Position-Locked Power Analysis.- Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations.- A Generalized Method of Differential Fault Attack Against AES Cryptosystem.- Special Purpose Hardware.- Breaking Ciphers with COPACOBANA -A Cost-Optimized Parallel Code Breaker.- Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware.- Efficient Algorithms for Embedded Processors.- Implementing Cryptographic Pairings on Smartcards.- SPA-Resistant Scalar Multiplication on Hyperelliptic Curve Cryptosystems Combining Divisor Decomposition Technique and Joint Regular Form.- Fast Generation of Prime Numbers on Portable Devices: An Update.- Side Channels II.- A Proposition for Correlation Power Analysis Enhancement.- High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching.- Cache-Collision Timing Attacks Against AES.- Provably Secure S-Box Implementation Based on Fourier Transform.- Invited Talk II.- The Outer Limits of RFID Security.- Hardware Attacks and Countermeasures II.- Three-Phase Dual-Rail Pre-charge Logic.- Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage.- Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style.- Efficient Hardware I.- Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors.- NanoCMOS-Molecular Realization of Rijndael.- Improving SHA-2 Hardware Implementations.- Trusted Computing.- Offline Hardware/Software Authentication for Reconfigurable Platforms.- Side Channels III.- Why One Should Also Secure RSA Public Key Elements.- Power Attack on Small RSA Public Exponent.- Unified Point Addition Formulæ and Side-Channel Attacks.- Hardware Attacks and Countermeasures III.- Read-Proof Hardware from Protective Coatings.- Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits.- Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks.- Invited Talk III.- Challenges for Trusted Computing.- Efficient Hardware II.- Superscalar Coprocessor for High-Speed Curve-Based Cryptography.- Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller.- FPGA Implementation of Point Multiplication on Koblitz Curves Using Kleinian Integers.


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