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Embedded system design, topics, techniques, and trends : IFIP TC10 Working ConferenceInternational Embedded Systems Symposium (IESS) : May 30-June 1, 2007, Irvine (CA), USA

Embedded system design, topics, techniques, and trends : IFIP TC10 Working ConferenceInternational Embedded Systems Symposium (IESS) : May 30-June 1, 2007, Irvine (CA), USA

자료유형
단행본
개인저자
Rettberg, Achim.
서명 / 저자사항
Embedded system design, topics, techniques, and trends : IFIP TC10 Working ConferenceInternational Embedded Systems Symposium (IESS) : May 30-June 1, 2007, Irvine (CA), USA / edited by Achim Rettberg ... [et al.].
발행사항
New York :   Springer ,   2007.  
형태사항
xvi, 444 p. : ill. ; 25 cm.
총서사항
International Federation for Information Processing
ISBN
9780387722573 (alk. paper)
서지주기
Includes bibliographical references.
일반주제명
Embedded computer systems -- Congresses. Automotive computers -- Congresses.
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010 ▼a 2007925211
020 ▼a 9780387722573 (alk. paper)
035 ▼a (KERIS)BIB000011048326
040 ▼a DLC ▼c DLC ▼d DLC ▼d 211048 ▼d 244002
050 0 0 ▼a TK7895.E42 ▼b I34 2007
082 0 4 ▼a 005.3 ▼2 22
090 ▼a 005.3 ▼b E532
245 0 0 ▼a Embedded system design, topics, techniques, and trends : ▼b IFIP TC10 Working ConferenceInternational Embedded Systems Symposium (IESS) : May 30-June 1, 2007, Irvine (CA), USA / ▼c edited by Achim Rettberg ... [et al.].
260 ▼a New York : ▼b Springer , ▼c 2007.
300 ▼a xvi, 444 p. : ▼b ill. ; ▼c 25 cm.
490 1 ▼a International Federation for Information Processing
504 ▼a Includes bibliographical references.
650 0 ▼a Embedded computer systems ▼v Congresses.
650 0 ▼a Automotive computers ▼v Congresses.
700 1 ▼a Rettberg, Achim.
711 2 ▼a IFIP TC10 Working Conference: International Embedded Systems Symposium ▼d (2007 : ▼c Irvine, Calif.)
830 0 ▼a International Federation for Information Processing (Series) ▼v 231

소장정보

No. 소장처 청구기호 등록번호 도서상태 반납예정일 예약 서비스
No. 1 소장처 세종학술정보원/과학기술실/ 청구기호 005.3 E532 등록번호 151243859 도서상태 대출가능 반납예정일 예약 서비스 C

컨텐츠정보

목차

Validation and Verification.- Requirements and Concepts for Transaction Level Assertion Refinement.- Using a Runtime Measurement Device with Measurement-Based WCET Analysis.- Implementing Real-Time Algorithms by using the AAA Prototyping Methodology.- Run-Time efficient Feasibility Analysis of Uni-Processor Systems with Static Priorities.- Approach for a Formal Verification of a Bit-serial Pipelined Architecture.- Automotive Applications.- Automotive System Optimization using Sensitivity Analysis.- Towards a Dynamically Reconfigurable Automotive Control System Architecture.- An OSEK/VDX-based Multi-JVM for Automotive Appliances.- Towards Dynamic Load Balancing for Distributed Embedded Automotive Systems.- Hardware Synthesis.- Automatic Data Path Generation from C code for Custom Processors.- Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures.- An Interactive Design Environment for C-based High-Level Synthesis.- Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning.- Embedded Vertex Shader in FPGA.- Specification and Partitioning.- A Hybrid Approach for System-Level Design Evaluation.- Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs.- An Interactive Model Re-Coder for Efficient SoC Specification.- Constrained and Unconstrained Hardware-Software Partitioning using Particle Swarm Optimization Technique.- Design Methodologies.- Using Aspect-Oriented Concepts in the Requirements Analysis of Distributed Real-Time Embedded Systems.- Smart Speed TechnologyTM.- Embedded Software.- Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt Services.- Reducing the Code Size of Retimed Software Loops under Timing and Resource Constraints.- Identification and Removal of Program Slice Criteria for Code Size Reduction in Embedded Systems.- Configurable Hybridkernel for Embedded Real-Time Systems.- Embedded Software Development in a System-Level Design Flow.- Network on Chip.- Data Reuse Driven Memory and Network-On-Chip Co-Synthesis.- Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions.- Hardware Implementation of the Time-Triggered Ethernet Controller.- Error Containment in the Time-Triggered System-On-a-Chip Architecture.- Medical Applications.- Generic Architecture Designed for Biomedical Embedded Systems.- A Small High Performance Microprocessor Core Sirius for Embedded Low Power Designs, Demonstrated in a Medical Mass Application of an Electronic Pill(EPill®).- Distributed and Network Systems.- Utilizing Reconfigurable Hardware to Optimize Workflows in Networked Nodes.- Dynamic Software Update of Resource-Constrained Distributed Embedded Systems.- Configurable Medium Access Control for Wireless Sensor Networks.- Integrating Wireless Sensor Networks and the Grid through POP-C++.- Panel.- Modeling of Software-Hardware Complexes.- Modeling of Software-Hardware Complexes.- Enhancing a Real-Time Distributed Computing Component Model through Cross-Fertilization.- Modeling of Software-Hardware Complexes.- Software-Hardware Complexes: Towards Flexible Borders.- Tutorials.- Embedded SW Design Space Exploration and Automation using UML-Based Tools.- Medical Embedded Systems.


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