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FPGA implementations of neural networks

FPGA implementations of neural networks (Loan 2 times)

Material type
단행본
Personal Author
Ormondi, A. R Rajapakse, Jagath Chandana
Title Statement
FPGA implementations of neural networks / edited by A.R. Omondi, J.C. Rajapakse.
Publication, Distribution, etc
New York ;   London :   Springer ,   2005.  
Physical Medium
xii, 360 p. : ill. ; 25 cm.
ISBN
0387284850 (hbk.)
Bibliography, Etc. Note
Includes bibliographical references.
Subject Added Entry-Topical Term
Neural networks (Computer science) Field programmable gate arrays.
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008 050830s2005 nyua 000 0 eng
015 ▼a GBA575292 ▼2 bnb
020 ▼a 0387284850 (hbk.)
020 ▼z 9780387284859
020 ▼z 9780387284873
035 ▼a (KERIS)BIB000010353621
040 ▼a UKM ▼c UKM ▼d 211046 ▼d 211046 ▼d 244002
082 0 4 ▼a 006.32 ▼2 22
090 ▼a 006.32 ▼b F796
245 0 0 ▼a FPGA implementations of neural networks / ▼c edited by A.R. Omondi, J.C. Rajapakse.
260 ▼a New York ; ▼a London : ▼b Springer , ▼c 2005.
300 ▼a xii, 360 p. : ▼b ill. ; ▼c 25 cm.
504 ▼a Includes bibliographical references.
650 0 ▼a Neural networks (Computer science)
650 0 ▼a Field programmable gate arrays.
700 1 ▼a Ormondi, A. R
700 1 ▼a Rajapakse, Jagath Chandana

Holdings Information

No. Location Call Number Accession No. Availability Due Date Make a Reservation Service
No. 1 Location Sejong Academic Information Center/Science & Technology/ Call Number 006.32 F796 Accession No. 151217063 Availability Available Due Date Make a Reservation Service C

Contents information

Table of Contents

Preface. 1. FPGA Neurocomputers; A.R.Omondi, J.C.Rajapakse and M.Bajger. 2. Arithmetic precision for BP networks; M.Moussa, S.Areibi and K.Nichols. 3. FPNA: Concepts and properties; B.Girau . 4. FPNA: Applications and implementations; B.Girau . 5. Back-Propagation Algorithms Achieving 5 GOPS on the VirtexE; K.Paul and S.Rajopadhye . 6. FPGA Implementation of Very Large Associative Memories; D.Hammerstrom, C.Gao, S.Zhu and M.Butts . 7. FPGA Implementations of Neocognitrons; A.Noriaki Ide and J.Hiroki Saito . 8. Self Organizing Feature Map for Color Quantization on FPGA; C-H.Chang, M.Shibu and R.Xiao . 9. Implemention of Self-Organizing Feature Maps in Reconfigurable Hardware; M.Porrmann, U.Witkowski and U.Ruckert . 10. FPGA Implementation of a Fully and Partially Connected MLP; A.Canas, E.M.Ortigosa, E.Ros and P.M.Ortigosa . 11. FPGA Implementation of Non-Linear Predictors; R.Gadea-Girones and A.Ramrez-Agundis . 12. The REMAP Reconfigurable Architecture: a retrospective; L.Bengtsson, A.Linde, T.Nordstrom, B.Svensson and M.Taveniku .


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