| 000 | 00880camuu22002654a 4500 | |
| 001 | 000045252898 | |
| 005 | 20060512144257 | |
| 008 | 030418s2003 maua b 001 0 eng | |
| 010 | ▼a 2003051289 | |
| 020 | ▼a 1402074166 | |
| 035 | ▼a (KERIS)REF000007248114 | |
| 040 | ▼a DLC ▼c DLC ▼d DLC ▼d 211009 | |
| 042 | ▼a pcc | |
| 050 | 0 0 | ▼a QA76.9.A73 ▼b G53 2003 |
| 082 | 0 0 | ▼a 004.2/2 ▼2 21 |
| 090 | ▼a 004.22 ▼b G489c | |
| 100 | 1 | ▼a Gilreath, William F. |
| 245 | 1 0 | ▼a Computer architecture : ▼b a minimalist perspective / ▼c William F. Gilreath, Phillip A. Laplante. |
| 260 | ▼a Boston, Mass. : ▼b Kluwer Academic Publishers , ▼c 2003. | |
| 300 | ▼a xiv, 220 p. : ▼b ill. ; ▼c 25 cm. | |
| 504 | ▼a Includes bibliographical references (p. 205-211) and index. | |
| 650 | 0 | ▼a Computer architecture. |
| 700 | 1 | ▼a Laplante, Phillip A. |
| 945 | ▼a KINS |
소장정보
| No. | 소장처 | 청구기호 | 등록번호 | 도서상태 | 반납예정일 | 예약 | 서비스 |
|---|---|---|---|---|---|---|---|
| No. 1 | 소장처 과학도서관/Sci-Info(2층서고)/ | 청구기호 004.22 G489c | 등록번호 121127523 | 도서상태 대출가능 | 반납예정일 | 예약 | 서비스 |
컨텐츠정보
목차
Preface. Acknowledgements. - 1: One Instruction Set Computing. 1.1. What is One Instruction Set Computing? 1.2. Why Study OISC? 1.3. A Look Ahead. 1.4. Exercises. 2: Instruction Sets. 2.1. Elements of an Instruction. 2.2. Operands. 2.3. Instruction Formats. 2.4. Core Set of Instructions. 2.5. Addressing Modes. 2.6. Exercises. - 3: Types of Computer Architecture. 3.1. Overview. 3.2.A Simple Taxonomy. 3.3. Accumulator. 3.4. Register-Memory. 3.5. Register-Oriented. 3.6. Exercises. - 4: Evolution of Instruction Sets. 4.1. Motivation. 4.2. Evolution of Microprocessors. 4.3. Timeline. 4.4. Exercises. - 5: CISC, RISC, OISC. 5.1. CISC versus RISC. 5.2. Is OISC a CISC or a RISC? 5.3. Processor Complexity. 5.4. Exercises. - 6: OISC Architectures. 6.1. Single Instruction Types. 6.2. MOVE. 6.3. Comparing OISC Models. 6.4. Variants of SBN and MOVE. 6.5. OISC Continuum. 6.6. Exercises. - 7: Historical Review of OISC. 7.1. Subtract and Branch if Negative (SBN). 7.2. MOVE-Based. 7.3. Timeline. 7.4. Exercises. - 8: Instruction Set Completeness. 8.1. Instruction Set Completeness. 8.2. A Practical Approach to Determining Completeness. 8.3. Completeness of Two OISCs. 8.4. Exercises. - 9: OISC Mappings. 9.1. Mapping OISC to Conventional Architectures. 9.2. Synthesizing Instructions. 9.3. Code Fragments. 9.4. Implementing OISC Using OISC. 9.5. Exercises. - 10: Parallel Architectures. 10.1. Von Neumann Bottleneck. 10.2. Parallel Processing. 10.3. Flynn's Taxonomy for Parallelism. 10.4. Exercises. - 11: Applications and Implementations. 11.1. OISC-Like Phenomena. 11.2. Field Programmable Gate Arrays. 11.3. Applications. 11.4. Image Processing. 11.5. Future Work with OISC. 11.6. Exercises. - Appendix A: A Generic Microprocessor and OISC. - Appendix B: One Instruction Set Computer Implementation. - Appendix C: Dilation Code Implementation. - Appendix D: Compiler Output for Dilation. - Appendix E: OISC Equivalent of Dilation. Glossary. References. Index. About the Authors.
정보제공 :
