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Stream processor architecture

Stream processor architecture

Material type
단행본
Personal Author
Rixner, Scott.
Title Statement
Stream processor architecture / by Scott Rixner.
Publication, Distribution, etc
Boston :   Kluwer Academic Publishers,   c2002.  
Physical Medium
xiv, 120 p. : ill. ; 25 cm.
Series Statement
The Kluwer international series in engineering and computer science ; SECS 644
ISBN
0792375459 (alk. paper) :
Bibliography, Etc. Note
Includes bibliographical references (p. [113]-117) and index.
Subject Added Entry-Topical Term
Microprocessors. Computer architecture.
000 00881camuu2200253 a 4500
001 000001071920
005 20020503133536
008 010905s2002 maua b 001 0 eng
010 ▼a 2001038986
020 ▼a 0792375459 (alk. paper) : ▼c EUR 107.00
040 ▼a DLC ▼c DLC ▼d DLC ▼d 244002
049 0 ▼l 151124934
050 0 0 ▼a QA76.5 ▼b .R493 2002
082 0 0 ▼a 004.2/2 ▼2 21
090 ▼a 004.22 ▼b R626s
100 1 ▼a Rixner, Scott.
245 1 0 ▼a Stream processor architecture / ▼c by Scott Rixner.
260 ▼a Boston : ▼b Kluwer Academic Publishers, ▼c c2002.
300 ▼a xiv, 120 p. : ▼b ill. ; ▼c 25 cm.
440 4 ▼a The Kluwer international series in engineering and computer science ; ▼v SECS 644
504 ▼a Includes bibliographical references (p. [113]-117) and index.
650 0 ▼a Microprocessors.
650 0 ▼a Computer architecture.

Holdings Information

No. Location Call Number Accession No. Availability Due Date Make a Reservation Service
No. 1 Location Sejong Academic Information Center/Science & Technology/ Call Number 004.22 R626s Accession No. 151124934 Availability Available Due Date Make a Reservation Service C M

Contents information

Table of Contents

Foreword. Acknowledgements. 1: Introduction. 1.1 Stream Architecture. 1.2. The Imagine Media Processor. 1.3. Contributions. 1.4. Overview. 2: Background. 2.1. Special-purpose Media Processors. 2.2. Programmable Media Processors. 2.3. Vector Processors. 2.4. Stream Processors. 2.5. Storage Hierarchy. 2.6. DRAM Access Scheduling. 2.7. Summary. 3: Media Processing Applications. 3.1. Media Processing. 3.2. Sample Applications. 3.3. Application Characteristics. 4: The Imagine Stream Processor. 4.1. Stream Processing. 4.2. Architecture. 4.3. Programming Model. 4.4. Implementation. 4.5. Scalability and Extensibility. 5: Data Bandwidth Hierarchy. 5.1. Overview. 5.2. Communication Bottlenecks. 5.3. Register Organization. 5.4. Evaluation. 5.5. Summary. 6: Memory Access Scheduling. 6.1. Overview. 6.2. Modern DRAM. 6.3. Memory Access Scheduling. 6.4. Evaluation. 6.5. Summary. 7: Conclusions. 7.1. Imagine Summary. 7.2. Future Architectures. References. Index.


Information Provided By: : Aladin

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