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Computer architecture : complexity and correctness

Computer architecture : complexity and correctness

Material type
단행본
Personal Author
Muller, Silvia M. Paul, Wolfgang J. , 1951-
Title Statement
Computer architecture complexity and correctness / Silvia M. Mueller, Wolfgang J. Paul.
Publication, Distribution, etc
Berlin ;   New York :   Springer,   2000.  
Physical Medium
xiii, 553 p. ; 25 cm.
ISBN
3540674810 (alk. paper)
Bibliography, Etc. Note
Includes bibliographical references (p. [543]-547) and index.
Subject Added Entry-Topical Term
Computer architecture.
000 00849camuu22002534a 4500
001 000000799874
005 20030404111245
008 000428s2000 gw b 001 0 eng
010 ▼a 00033827
020 ▼a 3540674810 (alk. paper)
040 ▼a DLC ▼c DLC ▼d OHX ▼d C#P ▼d UKM ▼d OCLCQ ▼d 211009
042 ▼a pcc
049 1 ▼l 111229959
050 0 0 ▼a QA76.9.A73 ▼b M845 2000
082 0 0 ▼a 004.2/2 ▼2 21
090 ▼a 004.22 ▼b M958c
100 1 ▼a Muller, Silvia M.
245 1 0 ▼a Computer architecture ▼b complexity and correctness / ▼c Silvia M. Mueller, Wolfgang J. Paul.
260 ▼a Berlin ; ▼a New York : ▼b Springer, ▼c 2000.
300 ▼a xiii, 553 p. ; ▼c 25 cm.
504 ▼a Includes bibliographical references (p. [543]-547) and index.
650 0 ▼a Computer architecture.
700 1 ▼a Paul, Wolfgang J. , ▼d 1951-

Holdings Information

No. Location Call Number Accession No. Availability Due Date Make a Reservation Service
No. 1 Location Main Library/Western Books/ Call Number 004.22 M958c Accession No. 111229959 Availability Available Due Date Make a Reservation Service B M

Contents information

Table of Contents

1 Introduction.- 2 Basics.- 3 A Sequential DLX Design.- 4 Basic Pipelining.- 5 Interrupt Handling.- 6 Memory System Design.- 7 IEEE Floating Point Standard and Theory of Rounding.- 8 Floating Point Algorithms and Data Paths.- 9 Pipelined DLX Machine with Floating Point Core.- A DLX Instruction Set Architecture.- A.1 DLX Fixed-Point Core: FXU.- A.1.1 Instruction Formats.- A.1.2 Instruction Set Coding.- A.2 Floating-Point Extension.- A.2.1 FPU Register Set.- A.2.2 FPU Instruction Set.- B Specification of the FDLX Design.- B.1 RTL Instructions of the FDLX.- B.1.l Stage IF.- B.1.2 Stage ID.- B.1.3 Stage EX.- B.1.4 Stage M.- B.1.5 Stage WB.- B.2 Control Automata of the FDLX Design.- B.2.1 Automaton Controlling Stage ID.- B.2.2 Precomputed Control.


Information Provided By: : Aladin

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