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Computer architecture : complexity and correctness

Computer architecture : complexity and correctness

자료유형
단행본
개인저자
Muller, Silvia M. Paul, Wolfgang J. , 1951-
서명 / 저자사항
Computer architecture complexity and correctness / Silvia M. Mueller, Wolfgang J. Paul.
발행사항
Berlin ;   New York :   Springer,   2000.  
형태사항
xiii, 553 p. ; 25 cm.
ISBN
3540674810 (alk. paper)
서지주기
Includes bibliographical references (p. [543]-547) and index.
일반주제명
Computer architecture.
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020 ▼a 3540674810 (alk. paper)
040 ▼a DLC ▼c DLC ▼d OHX ▼d C#P ▼d UKM ▼d OCLCQ ▼d 211009
042 ▼a pcc
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082 0 0 ▼a 004.2/2 ▼2 21
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100 1 ▼a Muller, Silvia M.
245 1 0 ▼a Computer architecture ▼b complexity and correctness / ▼c Silvia M. Mueller, Wolfgang J. Paul.
260 ▼a Berlin ; ▼a New York : ▼b Springer, ▼c 2000.
300 ▼a xiii, 553 p. ; ▼c 25 cm.
504 ▼a Includes bibliographical references (p. [543]-547) and index.
650 0 ▼a Computer architecture.
700 1 ▼a Paul, Wolfgang J. , ▼d 1951-

소장정보

No. 소장처 청구기호 등록번호 도서상태 반납예정일 예약 서비스
No. 1 소장처 중앙도서관/서고6층/ 청구기호 004.22 M958c 등록번호 111229959 도서상태 대출가능 반납예정일 예약 서비스 B M

컨텐츠정보

목차

1 Introduction.- 2 Basics.- 3 A Sequential DLX Design.- 4 Basic Pipelining.- 5 Interrupt Handling.- 6 Memory System Design.- 7 IEEE Floating Point Standard and Theory of Rounding.- 8 Floating Point Algorithms and Data Paths.- 9 Pipelined DLX Machine with Floating Point Core.- A DLX Instruction Set Architecture.- A.1 DLX Fixed-Point Core: FXU.- A.1.1 Instruction Formats.- A.1.2 Instruction Set Coding.- A.2 Floating-Point Extension.- A.2.1 FPU Register Set.- A.2.2 FPU Instruction Set.- B Specification of the FDLX Design.- B.1 RTL Instructions of the FDLX.- B.1.l Stage IF.- B.1.2 Stage ID.- B.1.3 Stage EX.- B.1.4 Stage M.- B.1.5 Stage WB.- B.2 Control Automata of the FDLX Design.- B.2.1 Automaton Controlling Stage ID.- B.2.2 Precomputed Control.


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