Distributed and parallel embedded systems : IFIP WG10.3/WG10.5 International Workshop on Distributed and Parallel Embedded Systems (DIPES'98), October 5-6, 1998, Schloss Eringerfeld, Germany
| 000 | 00000pam u2200205 a 4500 | |
| 001 | 000000667910 | |
| 005 | 20151022113708 | |
| 008 | 990706s1999 maua b 100 0 eng | |
| 010 | ▼a 99037323 | |
| 020 | ▼a 0792386140 | |
| 040 | ▼a DLC ▼c DLC ▼d C#P ▼d UKM ▼d OHX ▼d 211009 | |
| 049 | ▼l 111161012 | |
| 050 | 0 0 | ▼a QA76.9.D5 ▼b I3477 1998 |
| 082 | 0 0 | ▼a 004/.36 ▼2 21 |
| 084 | ▼a 004.36 ▼2 DDCK | |
| 090 | ▼a 004.36 ▼b I23d | |
| 111 | 2 | ▼a IFIP WG10.3/WG10.5 International Workshop on Distributed and Parallel Embedded Systems ▼d (1998 : ▼c Schloss Eringerfeld, Germany) |
| 245 | 1 0 | ▼a Distributed and parallel embedded systems : ▼b IFIP WG10.3/WG10.5 International Workshop on Distributed and Parallel Embedded Systems (DIPES'98), October 5-6, 1998, Schloss Eringerfeld, Germany / ▼c edited by Franz J. Rammig. |
| 260 | ▼a Boston : ▼b Kluwer Academic, ▼c 1999. | |
| 300 | ▼a viii, 240 p. : ▼b ill. ; ▼c 25 cm. | |
| 490 | 1 | ▼a International Federation for Information Processing ; ▼v 25 |
| 504 | ▼a Includes bibliographical references. | |
| 650 | 0 | ▼a Electronic data processing ▼x Distributed processing ▼v Congresses. |
| 650 | 0 | ▼a Parallel processing (Electronic computers) ▼v Congresses. |
| 650 | 0 | ▼a Embedded computer systems ▼v Congresses. |
| 700 | 1 | ▼a Rammig, F. J. |
| 830 | 0 | ▼a International Federation for Information Processing (Series) ; ▼v 25. |
소장정보
| No. | 소장처 | 청구기호 | 등록번호 | 도서상태 | 반납예정일 | 예약 | 서비스 |
|---|---|---|---|---|---|---|---|
| No. 1 | 소장처 중앙도서관/서고6층/ | 청구기호 004.36 I23d | 등록번호 111161012 | 도서상태 대출가능 | 반납예정일 | 예약 | 서비스 |
컨텐츠정보
목차
Preface. Workshop Committee. 1. Formalisms for Embedded System Design. 2. Synthesis from Synchronous/Asynchronous Specification. 3. Partitioning and Load-Balancing. 4. Verification and Validation. 5. Design Environments. 6. Object Oriented Approaches.
정보제공 :
