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Microprocessors and microcomputer-based system design

Microprocessors and microcomputer-based system design (Loan 1 times)

Material type
단행본
Personal Author
Rafiquzzaman, Mohamed.
Title Statement
Microprocessors and microcomputer-based system design / Mohamed Rafiquzzaman.
Publication, Distribution, etc
Boca Raton, Fla. :   CRC Press,   c1990.  
Physical Medium
xvii, 1075 p. : ill. ; 25 cm.
ISBN
0849342759
Bibliography, Etc. Note
Includes bibliographical references (p. 1037-1042).
Subject Added Entry-Topical Term
System design. Microprocessors. Microcomputers.
000 00762camuuu200253 a 4500
001 000000479920
003 OCoLC
005 19970506102145.0
008 890828s1990 flua b 001 0 eng
010 ▼a 89023875 //r91
020 ▼a 0849342759
040 ▼a DLC ▼c DLC
049 ▼a ACSL ▼l 421116344
050 0 0 ▼a QA76.9.S88 ▼b R32 1990
082 0 0 ▼a 004.2/1 ▼2 20
090 ▼a 004.21 ▼b R138m
100 1 ▼a Rafiquzzaman, Mohamed.
245 1 0 ▼a Microprocessors and microcomputer-based system design / ▼c Mohamed Rafiquzzaman.
260 ▼a Boca Raton, Fla. : ▼b CRC Press, ▼c c1990.
300 ▼a xvii, 1075 p. : ▼b ill. ; ▼c 25 cm.
504 ▼a Includes bibliographical references (p. 1037-1042).
650 0 ▼a System design.
650 0 ▼a Microprocessors.
650 0 ▼a Microcomputers.

Holdings Information

No. Location Call Number Accession No. Availability Due Date Make a Reservation Service
No. 1 Location Science & Engineering Library/Sci-Info(Stacks2)/ Call Number 004.21 R138m Accession No. 421116344 Availability Available Due Date Make a Reservation Service B M

Contents information

Table of Contents


CONTENTS
Chapter 1 Introduction to Microprocessors and Microcomputer-Based Design = 1
  1.1 Evolution of the Microprocessor = 2
  1.2 Microcomputer Hardware = 3
    1.2.1 The System Bus = 3
    1.2.2 The Microprocessor = 4
    1.2.3 Memory Organization = 9
      1.2.3. a Introduction = 9
      1.2.3. b Main Memory Array Design = 12
      1.2.3. c Memory Management Concepts = 16
      1.2.3. d Cache Memory Organization = 22
    1.2.4 Input / Output (I / O) = 25
      1.2.4. a Programmed I / O = 26
      1.2.4. b Standard I / O Versus Memory-Mapped I / O = 28
      1.2.4. c Unconditional and Conditional Programmed I / O = 29
      1.2.4. d Typical Microcomputer I / O Circuits = 31
      1.2.4. e Interrupt Driven I / O = 33
      1.2.4. f Direct Memory Access (DMA) = 36
      1.2.4. g Summary of Microcomputer I / O Methods = 37
      1.2.4. h Coprocessors = 37
  1.3 Microcomputer System Software and Programming Concepts = 40
    1.3.1 System software = 40
    1.3.2 Programming Concepts = 41
      1.3.2. a Machine Language Programming = 41
      1.3.2. b Assembly Language Programming = 42
      1.3.2. c High-Level Language Programming = 43
  1.4 Microcomputer Typical Addressing Modes and Instructions = 44
    1.4.1 Introduction = 44
    1.4.2 Addressing Modes = 45
    1.4.3 Instruction Types = 47
  1.5 Basic Features of Microcomputer Development Systems = 48
  1.6 System Development Flowchart = 63
    1.6.1 Software Development = 64
    1.6.2 Hardware Development = 66
  1.7 Typical Practical Applications = 66
    1.7.1 Two-Position Controller = 66
    1.7.2 Personal Workstations = 68
    1.7.3 Fault-Tolerant Systems = 68
    1.7.4 Real-Time Controllers = 68
    1.7.5 Robotics = 69
    1.7.6 Summary = 69
  Questions and Problems = 69
Chapter 2 Intel 8085 = 73
  2.1 Introduction = 73
  2.2 Register Architecture = 75
  2.3 Memory Addressing = 77
  2.4 8085 Addressing Modes = 78
  2.5 8085 Instruction Set = 79
  2.6 Timing Methods = 112
  2.7 8085 Pins and Signals = 115
  2.8 808S Instruction Timing and Execution = 122
    2.8.1 Basic System Timing = 123
    2.8.2 8085 Memory Read (IO / M ? =0, RD ? = 0) and I / O Read (IO / M ? =1, RD ? = 0) = 125
    2.8.3 8085 Memory Write (IO / M ? =0, WR ? = 0) and I / O Write (IO / M ? =1, WR ? = 0) = 125
  2.9 8085 Input / Output (I / O) = 130
    2.9.1 8085 Programmed I / O = 130
      2.9.1. a 8355/8755 I / O Ports = 130
      2.9.1. b 8155/8156 I / O Ports = 134
    2.9.2 8085 Interrupt System = 141
    2.9.3 8085 DMA = 153
    2.9.4 8085 SID and SOD Lines = 155
  2.10 8085-Based System Design = 156
  Questions and Problems = 160
Chapter 3 Intel 8086 = 167
  3.1 Introduction = 167
  3.2 Architecture = 170
  3.3 8086 Addressing Modes = 176
    3.3.1 Addressing Modes for Accessing Immediate and Register Data (Register and Immediate Modes) = 177
      3.3.1. a Register Addressing Mode = 177
      3.3.1. b Immediate Addressing Mode = 177
    3.3.2 Addressing Modes for Accessing Data in Memory (Memory Modes) = 177
      3.3.2. a Direct Addressing Mode = 178
      3.3.2. b Register Indirect Addressing Mode = 179
      3.3.2. c Based Addressing Mode = 179
      3.3.2. d Indexed Addressing Mode = 181
      3.3.2. e Based Indexed Addressing Mode = 183
      3.3.2. f String Addressing Mode = 185
    3.3.3 Addressing Modes for Accessing I / O Ports (I / O Modes) = 185
    3.3.4 Relative Addressing Mode = 185
    3.3.5 Implied Addressing Mode = 185
  3.4 8086 Instruction Set = 186
    3.4.1 Signed and Unsigned Conditional Branch Instructions = 211
    3.4.2 Conditional Jumps Affecting Individual Flags = 211
  3.5 8086 Instruction Format = 213
  3.6 8086 Assembler-Dependent Instructions = 216
  3.7 ASM-86 Assembler Pseudoinstructions = 216
    3.7.1 Segment and Ends = 219
    3.7.2 Assume Directive = 219
    3.7.3 DUP Directive = 219
  3.8 System Design Using 8086 = 227
    3.8.1 Pins and Signals = 227
    3.8.2 8086 Basic System Concepts = 234
      3.8.2. a 8086 Bus Cycle = 234
      3.8.2. b 8086 Address and Data Bus Concepts = 236
    3.8.3 Interfacing with Memories = 240
      3.8.3. a ROM and EPROM = 241
      3.8.3. b Static RAMs = 241
      3.8.3. c Dynamic RAM = 243
    3.8.4 8086 Programmed I / O = 243
      3.8.4. a Eight-Bit I / O Ports = 246
      3.8.4. b Sixteen-Bit I / O Ports = 246
    3.8.5 8086-Based Microcomputer = 247
  3.9 8086 Interrupt System = 255
    3.9.1 Predefined Interrupts (0 to 4) = 257
    3.9.2 User-Defined Software Interrupts = 258
    3.9.3 User-Defined Hardware (Maskable Interrupts) = 258
  3.10 8086 DMA = 262
  3.11 8089 I/O Processor = 262
  Questions and Problems = 265
  8086 Instructions Tables = 268
    8086 Data Transfer Instructions = 268
    8086 I / O Introduction = 271
    Address Object Transfers = 272
    8086 Flag Register Instructions = 273
    Arithmetic Instructions = 274
    Logical Instructions = 281
    String Instructions = 290
    Unconditional Transfers = 292
    Conditional Branch Instructions = 299
    Loop Instructions = 301
    Interrupt Instructions = 302
    Processor Control Instructions = 303
Chapter 4 Intel 80186 / 80286 / 80386 = 305
  4.1 Intel 80186 and 80286 = 305
    4.1.1 Intel 80186 = 305
    4.1.2 Intel 80286 = 312
      4.1.2. a 80286 Memory Management = 317
      4.1.2. b Protection = 321
  4.2 Intel 80386 = 328
    4.2.1 Basic 80386 Programming Model = 332
      4.2.1. a Memory Organization and Segmentation = 333
      4.2.1. b Data Types = 333
      4.2.1. c 80386 Registers = 334
      4.2.1. d Instruction Format = 337
      4.2.1. e 80386 Addressing Modes = 337
    4.2.2 80386 Instruction Set = 341
      4.2.2. a Arithmetic Instructions = 356
      4.2.2. b Bit Instructions = 356
      4.2.2. c Byte-Set-On Condition Instructions = 358
      4.2.2. d Conditional Jumps and Loop = 359
      4.2.2. e Data Transfer = 360
      4.2.2. f Flag Control = 362
      4.2.2. g Logical = 362
      4.2.2. h String = 363
      4.2.2. i Table Look-Up Translation Instruction = 365
      4.2.2. j High-Level Language Instructions = 365
    4.2.3 Memory Organization = 368
    4.2.4 I / O Space = 370
    4.2.5 80386 Interrupt = 370
    4.2.6 80386 Reset and Initialization = 374
    4.2.7 Testability = 374
    4.2.8 Debugging = 375
    4.2.9 80386 Pins and Signals = 375
    4.2.10 80386 Bus Transfer Technique = 382
    4.2.11 80386 Read and Write Cycles = 383
    4.2.12 80386 Modes = 386
      4.2.12. a 80386 Real Mode = 386
      4.2.12. b Protected Mode = 388
      4.2.12. c Virtual 8086 Mode = 393
  Questions and Problems = 394
Chapter 5 Motorola MC68000 = 399
  5.1 Introduction = 399
  5.2 68000 Programming Model = 402
  5.3 68000 Addressing Structure = 403
  5.4 68000 Instruction Format = 404
  5.5 68000 Addressing Modes = 407
    5.5.1 Register Direct Addressing = 407
    5.5.2 Address Register Indirect Addressing = 409
    5.5.3 Absolute Addressing = 411
    5.5.4 Program Counter Relative Addressing = 412
    5.5.5 Immediate Data Addressing Mode = 412
    5.5.6 Implied Addressing = 413
  5.6 68000 Instruction Set = 414
    5.6.1 Data Movement Instructions = 422
      5.6.1. a MOVE Instructions = 425
      5.6.1. b EXG and SWAP Instructions = 427
      5.6.1. c LEA and PEA Instructions = 427
      5.6.1. d LINK and UNLK Instructions = 428
    5.6.2 Arithmetic Instructions = 429
      5.6.2. a Addition and Subtraction Instructions = 432
      5.6.2. b Multiplication and Division Instructions = 432
      5.6.2. c Compare, Clear, and Negate Instructions = 433
      5.6.2. d Extended Arithmetic Instructions = 433
      5.6.2. e Test Instructions = 434
      5.6.2. f Test and Set Instruction = 434
    5.6.3 Logical Instructions = 436
    5.6.4 Shift and Rotate Instructions = 437
    5.6.5 Bit Manipulation Instructions = 440
    5.6.6 Binary-Coded Decimal Instruction = 441
    5.6.7 Program Control Instructions = 442
      5.6.7. a Using 68000 Registers = 447
      5.6.7. b Using 68000 Stack = 447
      5.6.7. c Using Parameter Areas in Memory = 448
      5.6.7. d By Coding Argument Values after Subroutine Call = 449
    5.6.8 System Control Instructions = 452
    5.6.9 Stacks and Queues = 455
      5.6.9. a Stacks = 455
      5.6.9. b Queues = 458
  5.7 68000 Pins and Signals = 465
    5.7.1 Synchronous and Asynchronous Control Lines = 468
    5.7.2 System Control Lines = 471
    5.7.3 Interrupt Control Lines = 477
    5.7.4 DMA Control Lines = 477
    5.7.5 Status Lines = 477
  5.8 68000 System Diagram = 478
  5.9 Timing Diagrams = 479
  5.10 68000 Memory Interface = 482
  5.11 68000 Programmed I/O = 486
    5.11.1 68000-68230 Interface = 487
    5.11.2 Motorola 68000-6820 Interface = 505
  5.12 68000 / 2716 / 6116 / 6821-Based Microcomputer = 509
  5.13 68000 Interrupt I/O = 515
    5.13.1 External Interrupts = 515
    5.13.2 Internal Interrupts = 521
    5.13.3 68000 Exception Map = 521
    5.13.4 68000 Interrupt Address Vector = 521
    5.13.5 An Example of Autovector and Nonautovector Interrupts = 522
    5.13.6 Interfacing of a Typical A/D Converter to the 68000 Using Autovector and Nonautovector Interrupts = 523
  5.14 68000 DMA = 524
  5.15 68000 Exception Handling = 526
  5.16 Multiprocessing with 68000 Using the TAS Instruction and AS ? (Address Strobe) Signal = 528
    5.16.1 68000 Minimum Subsystem = 530
    5.16.2 Shared Memory and Buffer Control Logic = 530
    5.16.3 Arbiter = 530
    5.16.4 Digital Delay Lines = 534
  5.17 68000 Nanomemory = 536
  5.18 Basic Differences between the 68000, 68008, 68010, and 68012 = 539
  Questions and Problems = 543
Chapter 6 Motorola MC68020 = 549
  6.1 Introduction = 549
  6.2 Peripheral Support and Applications = 554
  6.3 Functional Block Description = 555
  6.4 Programmer's Model = 556
  6.5 Data Types, Organization, and CPU Space Cycle = 558
  6.6 MC68020 Addressing Modes = 562
    6.6.1 Address Register Indirect (ARI) with Index (Scaled) and 8-Bit Displacement = 562
    6.6.2 ARI with Index (Base Displacement, bd : Value 0 or 16 Bits or 32 Bits) = 562
    6.6.3 Memory Indirect = 565
    6.6.4 Memory Indirect with PC = 567
      6.6.4. a PC Indirect with Index (8-Bit Displacement) = 568
      6.6.4. b PC Indirect with Index (Base Displacement) = 568
      6.6.4. c PC Indirect (Postindexed) = 569
      6.6.4. d PC Indirect (Preindexed) = 569
  6.7 Instructions = 572
    6.7.1 New Privileged Move Instruction = 577
    6.7.2 Return and Delocate Instruction = 580
    6.7.3 CHK / CHK2 and CMP / CMP2 Instructions = 582
    6.7.4 Trap on Condition Instructions = 587
    6.7.5 Bit Field Instructions = 588
    6.7.6 Pack and Unpack Instructions = 592
    6.7.7 Multiplication and Division Instructions = 595
    6.7.8 MC68000 Enhanced Instructions = 599
  6.8 MC68020 Pins and Signals = 602
  6.9 MC68020 Timing Diagrams = 626
  6.10 Exception Processing = 629
  6.11 MC68020 Memory and I / O Interfaces = 644
  6.12 MC68020 System Design = 650
  Questions and Problems = 657
Chapter 7 MC68020-Advanced Topics = 665
  7.1 68020 Advanced Instructions = 665
    7.1.1 Break point Instruction = 665
    7.1.2 Call Module / Return from Module Instructions = 670
    7.1.3 Compare, Swap, and CAS Instructions = 680
    7.1.4 Coprocessor Instructions = 692
  7.2 MC68020 Cache / Pipelined Architecture and Operation = 697
  7.3 MC68020 Virtual Memory = 702
  7.4 MC68020 Coprocessor Interface = 704
    7.4.1 MC68881 Floating-Point Coprocessor = 713
      7.4.1. a MOVEs = 719
      7.4.1. b MOVE Multiple Registers = 719
      7.4.1. c Monadic = 719
      7.4.1. d Dyadic Instructions = 721
      7.4.1. e BRANCH, Set, or Trap-On Condition = 722
      7.4.1. f Miscellaneous Instructions = 722
    7.4.2 MC68851 MMU = 735
  Questions and Problems = 739
Chapter 8 Motorola MC68030 and MC88100 = 743
  8.1 Motorola MC68030 = 743
    8.1.1 MC68030 Block Diagram = 744
    8.1.2 MC68030 Programming Model = 745
    8.1.3 MC68030 Data Types, Addressing Modes, and Instructions = 747
      8.1.3. a PMOVE Rn, (EA) or (EA), Rn = 748
      8.1.3. b PTEST = 748
      8.1.3. c PLOAD = 749
      8.1.3. d PFLUSH = 751
    8.1.4 MC68030 Cache = 751
    8.1.5 68030 Pins and Signals = 757
    8.1.6 MC68030 Read and Write Timing Diagrams = 757
    8.1.7 MC68030 On-Chip Memory Management Unit = 766
      8.1.7. a MMU Basics = 766
      8.1.7. b 68030 On-Chip MMU = 772
  8.2 Motorola MC88100 32-Bit RISC (Reduced Instruction Set Computer) Microprocessor = 786
    8.2.1 Basics of RISC = 786
    8.2.2 Basic Features of the 88100 RISC Microprocessor = 787
    8.2.3 88100 / 88200 Interface = 788
    8.2.4 88100 Registers = 790
    8.2.5 88100 Data Types, Addressing Modes, and Instructions = 800
    8.2.6 88100 Pins and Signals = 819
    8.2.7 88100 Exception Processing = 819
  Questions and Problems = 830
Chapter 9 Peripheral Interfacing = 835
  9.1 Basics of Keyboard and Display Interface to Microprocessor = 835
    9.1.1 Hexadecimal Keyboard / Display Interface to the 8085 = 839
    9.1.2 Intel 8279 Keyboard / Display Controller Chip = 845
      9.1.2. a Introduction = 845
      9.1.2. b Interfacing to the 8085 = 845
      9.1.2. c Interfacing to Keyboard Display Hardware = 849
      9.1.2. d Software Interface = 854
    9.1.3 An 8085-Based Microcomputer Using the 8279 for Keyboard Display Interface = 859
      9.1.3. a Statement of the Problem = 859
      9.1.3. b Hardware Description = 860
      9.1.3. c Software Description = 866
  9.2 DMA Controllers = 877
  9.3 Printer Interface = 884
    9.3.1 LRC7040 Printer Interface Using Direct Microcomputer Control = 886
    9.3.2 LRC7040 Printer Interface to a Microcomputer Using the 8295 Printer Controller Chip = 887
      9.3.2. a 829e Parallel Interface = 889
      9.3.2. b 8295 Serial Mode = 891
  9.4 CRT (Cathode Ray Tube) Controller and Graphics Controller Chips = 892
    9.4.1 CRT Fundamentals = 892
    9.4.2 Intel 8275 CRT Controller = 895
    9.4.3 Intel 82786 Graphics Controller = 897
  9.5 Floppy Disk Interface = 900
    9.5.1 The Floppy Disk = 900
    9.5.2 The Floppy Disk Drive = 901
    9.5.3 The Floppy Disk Controller = 901
    9.5.4 Intel 82072 Floppy Disk Controller = 902
  9.6 Coprocessors = 905
    9.6.1 Intel 8087 = 905
    9.6.2 Intel 80287 = 906
    9.6.3 Intel 80387 = 907
  Questions and Problems = 908
Chapter 10 Design Problems = 911
  10.1 Design Problem No. 1 = 911
    10.1.1 Problem Statement = 911
    10.1.2 Objective = 911
    10.1.3 Operation = 911
    10.1.4 Hardware = 913
    10.1.5 Software = 913
  10.2 Design Problem No. 2 = 921
    10.2.1 Problem Statement = 921
    10.2.2 Solution No. 1 = 921
      10.2.2. a Hardware = 922
      10.2.2. b Microcomputer Development System = 925
      10.2.2. c Software = 928
    10.2.3 Solution No. 2 = 932
      10.2.3. a Hardware = 932
      10.2.3. b Software = 934
  Questions and Problems = 949
Appendix A HP 64000 = 957
Appendix B Motorola MC68000 and Support Chips-Data Sheets = 987
Appendix C Intel 8085, 8086, and Support Chips-Data Sheets = 999
Appendix D Glossary = 1017
Bibliography = 1037
Credits = 1043
Chip Index = 1045
General Index = 1051

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