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Computer and digital system architecture

Computer and digital system architecture (3회 대출)

자료유형
단행본
개인저자
Murray, William D.
서명 / 저자사항
Computer and digital system architecture / William D. Murray.
발행사항
Englewood Cliffs, N.J. :   Prentice-Hall,   c1990.  
형태사항
xii, 452 p. : ill. ; 25 cm.
ISBN
0131657216
일반주기
Includes index.  
서지주기
Includes bibliographical references (p. 434-445).
일반주제명
Computer architecture. Digital electronics.
000 00758camuuu200253 a 4500
001 000000109249
005 19980527100118.0
008 890426s1990 njua b 001 0 eng
010 ▼a 89008543
020 ▼a 0131657216
040 ▼a DLC ▼c DLC
049 1 ▼l 421104758 ▼f 과학
050 0 0 ▼a QA76.9.A73 ▼b M87 1990
082 0 0 ▼a 004.2/2 ▼2 20
090 ▼a 004.22 ▼b M984c
100 1 ▼a Murray, William D.
245 1 0 ▼a Computer and digital system architecture / ▼c William D. Murray.
260 ▼a Englewood Cliffs, N.J. : ▼b Prentice-Hall, ▼c c1990.
300 ▼a xii, 452 p. : ▼b ill. ; ▼c 25 cm.
500 ▼a Includes index.
504 ▼a Includes bibliographical references (p. 434-445).
650 0 ▼a Computer architecture.
650 0 ▼a Digital electronics.

소장정보

No. 소장처 청구기호 등록번호 도서상태 반납예정일 예약 서비스
No. 1 소장처 과학도서관/Sci-Info(2층서고)/ 청구기호 004.22 M984c 등록번호 421104758 도서상태 대출가능 반납예정일 예약 서비스 B M

컨텐츠정보

목차


CONTENTS
PREFACE
1 INTRODUCTION
 1.1 Why Study Computer Architecture? = 1
 1.2 Computers and Digital Systems = 2
 1.3 A Brief Look at History = 3
 1.4 A Baseline and Some Alternatives = 6
 1.5 Descriptive Mechanisms = 12
 1.6 Computer Performance Measures = 14
 1.7 Summary = 18
 1.8 Additional Reading = 18
 1.9 Course Projects = 20
2 DESIGN METHODOLOGY AND DESCRIPTIVE TOOLS = 21
 2.1 Outline of the Top-Down Approach = 21
 2.2 Requirements Analysis = 23
 2.3 Specifying the Design Objectives = 27
 2.4 Specific Architectural Decisions = 30
 2.5 Design Techniques and Tools = 32
 2.6 The Processor-Memory-Switch Descriptive System = 33
 2.7 Instruction-Set Processor Description = 38
 2.8 Description of Execution and Timing = 44
 2.9 Economics : Performance, Complexity and Cost = 50
 2.10 Summary = 50
 2.11 Additional Reading = 51
 2.12 Problems = 53
 2.13 Projects = 53
3 SYSTEM STRUCTURE (THE PMS LEVEL) = 54
 3.1 The Computer as a Digital System = 54
 3.2 Model Range and Expansion Potential = 55
 3.3 Alternative System Organizations = 61
 3.4 Intermodule and Intercomputer Communication = 67
 3.5 Input / Output Subsystems = 74
 3.6 Reconfiguring, Upgrading, and Reliability = 78
 3.7 Levels of Memory = 82
 3.8 Processors and Software Issues = 87
 3.9 System Performance and System Cost = 90
 3.10 Summary = 96
 3.11 Additional Reading = 97
 3.12 Problems = 98
 3.13 Projects = 100
4 THE MEMORY HIERARCHY
 4.1 The Various Forms of Computer Memory = 102
 4.2 Characteristics of Memory Devices = 103
 4.3 Processor Storage = 108
 4.4 Primary-Memory Organization = 110
 4.5 The Cache = 113
 4.6 Secondary and Archival Memory = 120
 4.7 Intermediate Stores and Secondary-Memory Buffering = 123
 4.8 Virtual-Memory Methods = 124
 4.9 Memory-Design Rationale and Examples = 128
 4.10 Detection and Correction of Errors = 131
 4.11 Summary = 134
 4.12 Additional Reading = 135
 4.13 Problems = 136
 4.14 Projects = 137
5 THE INSTRUCTION-SET PROCESSOR
 5.1 A Variety of Processor Organizations = 139
 5.2 Languages and Processors = 141
 5.3 Processors and Operating Systems = 152
 5.4 Processor State = 156
 5.5 Environments, Context Switching, and Interrupts = 166
 5.6 Representation of Data = 172
 5.7 Instruction Representation and Instruction Sets = 177
 5.8 Summary = 184
 5.9 Additional Reading = 187
 5.10 Problems = 187
 5.11 Projects = 192
6 PROCESSOR IMPLEMENTATION AND CONTROL = 193
 6.1 Hardware and Software Techniques = 193
 6.2 Virtual Machines and Actual Machines = 196
 6.3 Control of the Hareware = 200
 6.4 Fault Diagnosis and Maintenance = 215
 6.5 Reduced-Instruction-Set Computers (RISC) = 219
 6.6 Arithmetic and Other Function Units = 226
 6.7 Processor Performance Issues = 234
 6.8 Examples of Performance Evaluation = 240
 6.9 Summary = 245
 6.10 Additional Reading = 247
 6.11 Problems = 248
 6.12 Projects = 251
7 INPUT / OUTPUT AND OTHER PROCESSORS = 252
 7.1 Reducing Central-Processor Load = 252
 7.2 External Devices and Their Control = 254
 7.3 Peripheral-Device Controllers = 258
 7.4 Memory and Central-Processor Interfaces = 263
 7.5 Input / Output Processors = 275
 7.6 Memory Processors = 285
 7.7 "Hardware Engines" = 289
 7.8 Summary = 296
 7.9 Additional Reading = 297
 7.10 Problems = 298
 7.11 Projects = 299
8 PARALLEL COMPUTER SYSTEMS
 8.1 Extreme Performance Goals = 300
 8.2 Increasing Computer Performance = 302
 8.3 Vector and Array Processing = 309
 8.4 Pipeline and Arrsy Processors = 311
 8.5 Interconnection Revisited = 320
 8.6 Multiprocessors and Multicomputers = 326
 8.7 Performance of Parallel Systems = 334
 8.8 Summary = 341
 8.9 Additional Reading = 344
 8.10 Problems = 344
 8.11 Projects = 346
9 SPECIAL-PURPOSE COMPUTING SYSTEMS
 9.1 Problem Analogs = 347
 9.2 Responding to Requirements = 350
 9.3 Designing the System = 356
 9.4 Processing and Arithmetic Units = 360
 9.5 Alternativesin Control of Computation = 362
 9.6 Examples = 370
 9.7 Summary = 382
 9.8 Additional Reading = 383
 9.9 Problems = 383
 9.10 Projects = 384
10 SUMMARY AND PROGNOSIS
 10.1 Methodologies for Design and for Research = 385
 10.2 Technology and Architecture = 386
 10.3 InstructionSet Processors and Controls = 389
 10.4 System and Language Issues = 392
 10.5 Performance Measures = 395
 10.6 Outlook = 398
 10.7 Additional Reading = 399
 10.8 Ruture Projects = 400
APPENDIX A THE PMS AND ISP DESCRIPTIVE SYSTEMS = 401
 A.1 Introduction = 401
 A.2 Formal Definitions = 402
 A.3 PMS-Level Descriptions = 408
 A.4 ISP-Level Descriptions = 411
APPENDIX B SOME EXAMPLES OF INSTRUCTION-SET PROCESSORS = 412
REFERENCES = 434


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